Real time image processing with an analog vision chip system.
A linear analog network model is proposed to characterize the function of the outer retinal circuit in terms of the standard regularization theory. Inspired by the function and the architecture of the model, a vision chip has been designed using analog CMOS Very Large Scale Integrated circuit technology. In the chip, sample/hold amplifier circuits are incorporated to compensate for statistic transistor mismatches. Accordingly, extremely low noise outputs were obtained from the chip. Using the chip and a zero-crossing detector, edges of given images were effectively extracted in indoor illumination.
Kameda
S
S
Faculty of Computer Science and Systems Engineering, Kyushu Institute of Technology, Iizuka, Fukuoka, Japan.
Honda
A
A
Yagi
T
T
D000221:Adaptation, Ocular; D000465:Algorithms; D000818:Animals; D016477:Artifacts; D003199:Computer Systems; D003202:Computers, Analog; D004867:Equipment Design; D007091:Image Processing, Computer-Assisted / Q000295:instrumentation* / Q000379:methods*; D008029:Lighting; D016571:Neural Networks, Computer; D012160:Retina / Q000502:physiology; D014785:Vision, Ocular; D014795:Visual Pathways / Q000502:physiology; D014796:Visual Perception