title: The adiabatic anti-jitter circuit.
abstract: The anti-jitter circuit (AJC) [1], [2]-[4] is able to reduce phase noise and spurious content of any frequency source at sideband frequencies above a defined cut-off frequency. By contrast, a phase-locked loop (PLL) can only reduce the intrinsic phase noise of its output oscillator closer to carrier lower than a defined cut-off frequency. The AJC has no output oscillator, but its phase noise performance can be assessed as if it had [5]. This paper reports the invention of the adiabatic AJC (AAJC) [6]-[8], giving the AJC improved power consumption, frequency range, and maximum frequency of operation. The term "adiabatic" is adopted to indicate that the core part of the new circuit does not require a power supply. It takes power from the input source directly to create the sawtooth waveform that has considerably reduced time jitter on the longer of its two ramp waveforms. Discrete models of the AJC are now operational at 30 MHz, which is twice the 15-MHz operation previously reported. The cut-off frequency of suppression has been maintained at a few kiloHertz. Noise analysis now shows performance comparable with an LC oscillator is possible. SPICE simulations show potential operation up to 5 GHz. The AAJC is also cascadable up to the intrinsic (shot) noise limit. Shot noise can be reduced by feedback.
authors.affiliation: School of Electronic Engineering, Information Technology and Mathematics, University of Surrey, Guildford, Surrey, GU2 7XH, UK. m.underhill@surrey.ac.uk
authors.forename: M J
authors.initials: MJ
authors.lastname: Underhill