title: VLSI architectures for computing multiplications and inverses in GF(2m).
abstract: Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms.  There is a need for good multiplication and inversion algorithms that can be easily realized on VLSI chips.  Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation.  In this paper, a pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m).  With the simple squaring property of the normal basis representation used together with this multiplier, a pipeline architecture is developed for computing inverse elements in GF(2m).  The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable, and therefore, naturally suitable for VLSI implementation.
authors.affiliation: Jet Propulsion Laboratory, California Institute of Technology, Pasadena 91109, USA.
authors.forename: C C
authors.initials: CC
authors.lastname: Wang
authors.forename: T K
authors.initials: TK
authors.lastname: Truong
authors.forename: H M
authors.initials: HM
authors.lastname: Shao
authors.forename: L J
authors.initials: LJ
authors.lastname: Deutsch
authors.forename: J K
authors.initials: JK
authors.lastname: Omura
authors.forename: I S
authors.initials: IS
authors.lastname: Reed
mesh_terms: D000465:Algorithms; D003198:Computer Simulation; D003199:Computer Systems; D008433:Mathematics