title: Holographic voltage profiling on 75 nm gate architecture CMOS devices.
abstract: Voltage profiles of the source-drain region of a CMOS transistor with 75nm gate architecture taken from an off-the-shelf Intel PIII processor are presented. The sample preparation using a dual beam system is discussed as well as details of the electron optical setup of the microscope. Special attention is given to the analysis of the reconstructed holograms.
authors.affiliation: Department of Physics, 401 Nielson Physics Bldg., University of Tennessee, Knoxville 37996, USA. athesen@utk.edu
authors.forename: Alexander E
authors.initials: AE
authors.lastname: Thesen
authors.forename: Bernhard G
authors.initials: BG
authors.lastname: Frost
authors.forename: David C
authors.initials: DC
authors.lastname: Joy
mesh_terms: D004560:Electricity; D006696:Holography / Q000379:methods*; D008855:Microscopy, Electron, Scanning / Q000379:methods*; D014173:Transistors, Electronic