Holographic voltage profiling on 75 nm gate architecture CMOS devices.
Voltage profiles of the source-drain region of a CMOS transistor with 75nm gate architecture taken from an off-the-shelf Intel PIII processor are presented. The sample preparation using a dual beam system is discussed as well as details of the electron optical setup of the microscope. Special attention is given to the analysis of the reconstructed holograms.
Thesen
Alexander E
AE
Department of Physics, 401 Nielson Physics Bldg., University of Tennessee, Knoxville 37996, USA. athesen@utk.edu
Frost
Bernhard G
BG
Joy
David C
DC
D004560:Electricity; D006696:Holography / Q000379:methods*; D008855:Microscopy, Electron, Scanning / Q000379:methods*; D014173:Transistors, Electronic