Real-time synthesis of sparsely interconnected neural associative memories.
The problem of implementing associative memories using sparsely interconnected generalized Brain-State-in-a-Box (gBSB) network is addressed in this paper. In particular, a "designer" neural network that synthesizes the associative memories is proposed. An upper bound on the time required for the designer network to reach a solution is determined. A neighborhood criterion with toroidal geometry for the cellular gBSB network is analyzed, in which the number of adjacent cells is independent of the generic cell location. A design method of neural associative memories with prespecified interconnecting weights is presented. The effectiveness of the proposed synthesis method is demonstrated with numerical examples.
Chan
Hubert Y.
HY
School of Electrical and Computer Engineering, Box 540, Purdue University, West Lafayette, USA
Zak
Stanislaw H.
SH