Design and implementation of a modulator-based free-space optical backplane for multiprocessor applications.
Design and implementation of a free-space optical backplane for multiprocessor applications is presented. The system is designed to interconnect four multiprocessor nodes that communicate by using multiplexed 32-bit packets. Each multiprocessor node is electrically connected to an optoelectronic VLSI chip which implements the hyperplane interconnection architecture. The chips each contain 256 optical transmitters (implemented as dual-rail multiple quantum-well modulators) and 256 optical receivers. A rigid free-space microoptical interconnection system that interconnects the transceiver chips in a 512-channel unidirectional ring is implemented. Full design, implementation, and operational details are provided.
Department of Electrical and Computer Engineering, McGill University, 3480 University Street, Montreal, Quebec, Canada, H3A 2A7. andrew.kirk@mcgill.ca
Andrew G
AG
Kirk
David V
DV
Plant
Ted H
TH
Szymanski
Zvonko G
ZG
Vranesic
Frank A P
FA
Tooley
David R
DR
Rolston
Michael H
MH
Ayliffe
Frederic K
FK
Lacroix
Brian
B
Robertson
Eric
E
Bernier
Daniel F
DF
Brosseau