DPLL implementation in carrier acquisition and tracking for burst DS-CDMA receivers.
This paper presents the architectures, algorithms, and implementation considerations of the digital phase locked loop (DPLL) used for burst-mode packet DS-CDMA receivers. As we know, carrier offset is a rather challenging problem in CDMA system. According to different applications, different DPLL forms should be adopted to correct different maximum carrier offset in CDMA systems. One classical DPLL and two novel DPLL forms are discussed in the paper. The acquisition range of carrier offset can be widened by using the two novel DPLL forms without any performance degradation such as longer acquisition time or larger variance of the phase error. The maximum acquisition range is 1/(4T), where T is the symbol period. The design can be implemented by FPGA directly.
Guan
Yun-feng
YF
Institute of Information and Communication Engineering, Zhejiang University, Hangzhou 310027, China. yfguan69@yahoo.com
Zhang
Zhao-yang
ZY
Lai
Li-feng
LF
D000465:Algorithms; D003201:Computers; D004581:Electronics; D008962:Models, Theoretical; D055585:Physical Phenomena; D010825:Physics