A front-end automation tool supporting design, verification and reuse of SOC.
This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the Verilog code by more than a factor of 5, increase the efficiency of the front-end design, reduce the bug rate significantly. This tool can be used to enhance the reusability of an intellectual property model, and facilitate porting design for different platforms.
Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China.
Xiao-lang
XL
Yan
Long-li
LL
Yu
Jie-bing
JB
Wang
D000465:Algorithms; D017076:Computer-Aided Design; D004867:Equipment Design / Q000379:methods*; D019544:Equipment Failure Analysis / Q000379:methods*; D008838:Microcomputers; D011381:Programming Languages; D012984:Software; D012985:Software Design; D014584:User-Computer Interface