Si-C linked organic monolayers on crystalline silicon surfaces as alternative gate insulators.
Herein, the influence of silicon surface modification via Si-C(n)H(2n+1) (n=10,12,16,22) monolayer-based devices on p-type 100 and n-type 100 silicon is studied by forming MIS (metal-insulator-semiconductor) diodes using a mercury probe. From current density-voltage (J-V) and capacitance-voltage (C-V) measurements, the relevant parameters describing the electrical behavior of these diodes are derived, such as the diode ideality factor, the effective barrier height, the flatband voltage, the barrier height, the monolayer dielectric constant, the tunneling attenuation factor, and the fixed charge density (Nf). It is shown that the J-V behavior of our MIS structures could be precisely tuned via the monolayer thickness. The use of n-type silicon resulted in lower diode ideality factors as compared to p-type silicon. A similar flatband voltage, independent of monolayer thickness, was found, indicating similar properties for all silicon-monolayer interfaces. An exception was the C10-based monolayer device on p-type silicon. Furthermore, low values of N(f) were found for monolayers on p-type silicon (approximately 6 x 10(11) cm(-2)). These results suggest that Si--C linked monolayers on flat silicon may be a viable material for future electronic devices.
Faber
Erik J
EJ
BIOS, Lab-on-a-Chip Group, MESA+Research Institute, University of Twente, P.O. Box 217, 7500 AE Enschede, The Netherlands.
de Smet
Louis C P M
LC
Olthuis
Wouter
W
Zuilhof
Han
H
Sudhölter
Ernst J R
EJ
Bergveld
Piet
P
van den Berg
Albert
A