Silicon p-FETs from ultrahigh density nanowire arrays.
Statistical numbers of field-effect transistors (FETs) were fabricated from a circuit of 17-nm-wide, 34-nm-pitch Si nanowires boron doped at a level of 10(18) cm-3. Top-gated 4-microm-wide Si nanowire p-FETs yielded low off-currents (approximately 10(-12) A), high on/off ratios (10(5)-10(6)), good on current values (30 microA/microm), high mobilities (approximately 100 cm2/V-s), and low subthreshold swing values (approximately 80 mV/decade between 10(-12) and 10(-10) A increasing to 200 mV/decade between 10(-10)-10(-8) A).
Wang
Dunwei
D
Division of Chemistry and Chemical Engineering, California Institute of Technology, Pasadena, California 91125, USA.
Sheriff
Bonnie A
BA
Heath
James R
JR
D017097:Electric Impedance; D004559:Electric Wiring / Q000295:instrumentation* / Q000379:methods; D004867:Equipment Design; D019544:Equipment Failure Analysis; D008422:Materials Testing; D008839:Microelectrodes; D036103:Nanotechnology / Q000295:instrumentation* / Q000379:methods; D043942:Nanotubes / Q000737:chemistry* / Q000648:ultrastructure; D012825:Silicon / Q000737:chemistry*; D014173:Transistors, Electronic
D012825:Silicon