Design and implementation of High Performance Visual Stimulator for Brain Computer Interfaces.
An algorithm for implementing visual stimulators on generic computers has been developed for Brain Computer Interfaces (BCIs). It uses the hardware counter present in these systems to derive accurate timing. Simultaneous display of 20 patterns (e.g. 3&#215;3 checkerboards) modulated at different frequencies is possible. The pattern used for stimulating the Steady State Visual Evoked Potential (SSVEP) can be changed with ease. The stimulators are evaluated using software counters. High accuracy (less than 0.73% error) and precision (0.1% coefficient of variation) is recorded for 20 patterns set with frequencies between 6 Hz and 15 Hz.
Jaganathan
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Biomedical Engineering Division, Department of Applied Mechanics Indian Institute of Technology-Madras Chennai 600036, India.
Srihari Mukesh
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Ramasubba Reddy
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