The impact of arithmetic representation on implementing MLP-BP on FPGAs: a study.
In this paper, arithmetic representations for implementing multilayer perceptrons trained using the error backpropagation algorithm (MLP-BP) neural networks on field-programmable gate arrays (FPGAs) are examined in detail. Both floating-point (FLP) and fixed-point (FXP) formats are studied and the effect of precision of representation and FPGA area requirements are considered. A generic very high-speed integrated circuit hardware description language (VHDL) program was developed to help experiment with a large number of formats and designs. The results show that an MLP-BP network uses less clock cycles and consumes less real estate when compiled in an FXP format, compared with a larger and slower functioning compilation in an FLP format with similar data representation width, in bits, or a similar precision and range.
Savich
Antony W
AW
School of Engineering, University of Guelph, Guelph, ON NIG 2W1, Canada.
Moussa
Medhat
M
Areibi
Shawki
S
D003198:Computer Simulation; D017076:Computer-Aided Design; D004867:Equipment Design; D019544:Equipment Failure Analysis; D008962:Models, Theoretical; D016571:Neural Networks, Computer; D009716:Numerical Analysis, Computer-Assisted; D012815:Signal Processing, Computer-Assisted / Q000295:instrumentation*