A low-profile three-dimensional neural stimulating array with on-chip current generation.
This paper describes a low-profile silicon microelectrode array for selectively stimulating in the central nervous system. The array consists of a number of 64-site 8-channel planar CMOS probes, a platform to support the probes on the cortical surface, spacers to hold the probes orthogonal to the platform, and a hybrid chip for platform address decoding. It features integrated circuitry with on-chip current generation to deliver biphasic currents from -127 microA to +127 microA to selected sites with 1 microA resolution and fold-down structures to reduce the vertical rise above the cortex for chronic implants. The output stimulating current has a differential nonlinearity of less than 0.8LSBs and a biphasic mismatch of less than 0.23LSBs. The average power dissipation to generate full-range biphasic pulses with pulse widths of 100 micros at a repetition rate of 500 Hz is about 97 microW per channel. The probes and the hybrid chip are fabricated in a 3 microm, p-sub/n-epi/p-well 2P/1M micromachined CMOS technology; the other structures use a simplified passive process.
Yao
Y
Y
Engineering Research Center for Wireless Integrated MicroSystems, University of Michigan, Ann Arbor, MI 48109, USA.
Gulari
M
M
Hetke
J
J
Wise
K
K