title: Real-time system for high-image resolution disparity estimation.
abstract: We present the hardware implementation of a simple, fast technique for depth estimation based on phase measurement. This technique avoids the problem of phase warping and is much less susceptible to camera noise and distortion than standard block-matching stereo systems. The architecture exploits the parallel computing resources of FPGA devices to achieve a computation speed of 65 megapixels per second. For this purpose, we have designed a fine-grain pipeline structure that can be arranged with a customized frame-grabber module to process 52 frames per second at a resolution of 1280 x 960 pixels. We have measured the system's degradation due to bit quantization errors and compared its performance with other previous approaches. We have also used different Gabor-scale circuits, which can be selected by the user according to the application addressed and typical image structure in the target scenario.
authors.forename: Javier
authors.initials: J
authors.lastname: Díaz
authors.forename: Eduardo
authors.initials: E
authors.lastname: Ros
authors.forename: Richard
authors.initials: R
authors.lastname: Carrillo
authors.forename: Alberto
authors.initials: A
authors.lastname: Prieto
mesh_terms: D000465:Algorithms; D003199:Computer Systems; D004867:Equipment Design; D019544:Equipment Failure Analysis; D007089:Image Enhancement / Q000295:instrumentation* / Q000379:methods; D007090:Image Interpretation, Computer-Assisted / Q000295:instrumentation* / Q000379:methods; D021621:Imaging, Three-Dimensional / Q000295:instrumentation* / Q000379:methods; D016247:Information Storage and Retrieval / Q000379:methods*; D010780:Photogrammetry / Q000295:instrumentation* / Q000379:methods; D012815:Signal Processing, Computer-Assisted / Q000295:instrumentation*