title: PLL jitter reduction by utilizing a ferroelectric capacitor as a VCO timing element.
abstract: Ferroelectric capacitors have steadily been integrated into semiconductor processes due to their potential as storage elements within memory devices. Polarization reversal within ferroelectric capacitors creates a high nonlinear dielectric constant along with a hysteresis profile. Due to these attributes, a phase-locked loop (PLL), when based on a ferroelectric capacitor, has the advantage of reduced cycle-to-cycle jitter. PLLs based on ferroelectric capacitors represent a new research area for reduction of oscillator jitter.
authors.affiliation: Microelectronics Research Laboratories, Department of Electrical and Computer Engineering, University of Colorado, Colorado Springs, CO 80933-7150, USA.
authors.forename: Greg
authors.initials: G
authors.lastname: Pauls
authors.forename: Thottam S
authors.initials: TS
authors.lastname: Kalkur
mesh_terms: D025802:Electric Capacitance; D004581:Electronics / Q000295:instrumentation*; D004867:Equipment Design; D019544:Equipment Failure Analysis; D008280:Magnetics / Q000295:instrumentation*; D009991:Oscillometry / Q000295:instrumentation* / Q000379:methods; D015203:Reproducibility of Results; D012680:Sensitivity and Specificity; D013997:Time Factors