title: Selective plating for junction delineation in silicon nanowires.
abstract: The in situ growth of p-n junctions in silicon nanowires enables the fabrication of a variety of nanoscale electronic devices. We have developed a method for selective coating of Au onto n-type segments of silicon nanowire p-n junctions. Selective plating allows for quick verification of the position of p-n junctions along the nanowire using electron microscopy and allows for measurement of segment length.
authors: Department of Materials Science and Engineering and Materials Research Institute, The Pennsylvania State University, Steidle Building, University Park, Pennsylvania 16802, USA.
authors: Chad M
authors: CM
authors: Eichfeld
authors: Carolyn
authors: C
authors: Wood
authors: Bangzhi
authors: B
authors: Liu
authors: Sarah M
authors: SM
authors: Eichfeld
authors: Joan M
authors: JM
authors: Redwing
authors: Suzanne E
authors: SE
authors: Mohney
mesh_terms: D003460:Crystallization / Q000379:methods*; D046911:Macromolecular Substances / Q000737:chemistry; D008422:Materials Testing; D008968:Molecular Conformation; D049329:Nanostructures / Q000737:chemistry* / Q000648:ultrastructure*; D036103:Nanotechnology / Q000379:methods*; D010316:Particle Size; D012666:Semiconductors; D012825:Silicon / Q000737:chemistry*; D013499:Surface Properties
chemical_list: D046911:Macromolecular Substances; D012825:Silicon