title: Translating network models to parallel hardware in NEURON.
abstract: The increasing complexity of network models poses a growing computational burden. At the same time, computational neuroscientists are finding it easier to access parallel hardware, such as multiprocessor personal computers, workstation clusters, and massively parallel supercomputers. The practical question is how to move a working network model from a single processor to parallel hardware. Here we show how to make this transition for models implemented with NEURON, in such a way that the final result will run and produce numerically identical results on either serial or parallel hardware. This allows users to develop and debug models on readily available local resources, then run their code without modification on a parallel supercomputer.
authors.affiliation: Department of Computer Science, Yale University, New Haven, CT, USA. michael.hines@yale.edu
authors.forename: M L
authors.initials: ML
authors.lastname: Hines
authors.forename: N T
authors.initials: NT
authors.lastname: Carnevale
mesh_terms: D003198:Computer Simulation; D003199:Computer Systems; D008959:Models, Neurological; D016571:Neural Networks, Computer; D009474:Neurons / Q000502:physiology*; D011381:Programming Languages; D012984:Software