Extremely scaled 3-dimensional multiple-gate technologies for terabit era.
In order to make possible silicon-based, room-temperature operable devices having a feature size in the sub-5 nm range, an all-around gate FinFET having an extremely narrow gate-surrounded silicon fin with a floating body was proposed and fabricated. Sub-10 nm device issues such as short channel effects, punchthrough, source/drain series resistance, gate misalignment, and hot-carrier injection were intensively studied and optimized for the sub-5 nm structure. The sub-5 nm all-around gate FinFET with 3 nm fin width and 1.2 nm EOT was demonstrated for the first time.
Choi
Yang-Kyu
YK
School of Electrical and Computer Science, Division of Electrical Engineering, Korea Advanced Institute of Science and Technology, 373-1, Daejeon 305-701, Korea.
Kim
Kuk-Hwan
KH
Han
Jin-Woo
JW
Ryu
Seong-Wan
SW
Lee
Hyunjin
H
D003198:Computer Simulation; D004583:Electrons; D004867:Equipment Design; D019544:Equipment Failure Analysis; D008962:Models, Theoretical; D036103:Nanotechnology / Q000295:instrumentation* / Q000379:methods; D012815:Signal Processing, Computer-Assisted / Q000295:instrumentation*; D014173:Transistors, Electronic