title: Neural network implementation using bit streams.
abstract: A new method for the parallel hardware implementation of artificial neural networks (ANNs) using digital techniques is presented. Signals are represented using uniformly weighted single-bit streams. Techniques for generating bit streams from analog or multibit inputs are also presented. This single-bit representation offers significant advantages over multibit representations since they mitigate the fan-in and fan-out issues which are typical to distributed systems. To process these bit streams using ANNs concepts, functional elements which perform summing, scaling, and squashing have been implemented. These elements are modular and have been designed such that they can be easily interconnected. Two new architectures which act as monotonically increasing differentiable nonlinear squashing functions have also been presented. Using these functional elements, a multilayer perceptron (MLP) can be easily constructed. Two examples successfully demonstrate the use of bit streams in the implementation of ANNs. Since every functional element is individually instantiated, the implementation is genuinely parallel. The results clearly show that this bit-stream technique is viable for the hardware implementation of a variety of distributed systems and for ANNs in particular.
authors.affiliation: Department of Electrical and Computer Engineering University of Auckland, Auckland 1001, New Zealand. nd.patel@auckland.ac.nz
authors.forename: Nitish D
authors.initials: ND
authors.lastname: Patel
authors.forename: Sing Kiong
authors.initials: SK
authors.lastname: Nguang
authors.forename: George G
authors.initials: GG
authors.lastname: Coghill
mesh_terms: D003198:Computer Simulation; D003199:Computer Systems; D004867:Equipment Design; D019544:Equipment Failure Analysis; D008962:Models, Theoretical; D016571:Neural Networks, Computer; D012815:Signal Processing, Computer-Assisted / Q000295:instrumentation*