A pulse-based, parallel-element macromodel for ferroelectric capacitors.
A pulse-based behavioral model is proposed and implemented in HSPICE. Hysteresis-loop and pulse measurement results are used to extract the model parameters. The model accurately predicts the bitline voltage of a ferroelectric memory testchip.
Sheikholeslami
A
A
Department of Electrical and Computer Engineering, University of Toronto, Toronto, Ontario, Canada M5S 3G4. ali@eecg.toronto.edu
Gulak
P G
PG
Takauchi
H
H
Tamura
H
H
Yoshioka
H
H
Tamura
T
T