Faster power estimation of CMOS designs using vector compaction - a fractal approach.
Low power digital complementary metal oxide semiconductor (CMOS) circuit design requires accurate power estimation. In this paper, we present a compaction algorithm for generating compact vector sets to estimate power efficiently. Power can be estimated using dynamic (simulation) or static (statistical/probabilistic) techniques. Dynamic power estimation techniques simulate the design using a large input vector set for accurate estimation. However, the simulation time is prohibitively long for bigger designs with larger vector sets. The statistical methods, on the other hand, use analytical tools that make them faster but less accurate. To achieve the accuracy of dynamic power estimation and the speed of statistical methods, one approach is to generate a compact, representative vector set that has the same switching transition behavior as the original larger vector set. The compaction algorithm presented in this paper uses fractal concepts to generate such a compact vector set. The fractal technique quantifies correlation by a fractal parameter which can be determined faster than calculating correlation explicitly. Experimental results on circuits from the ISCAS85 and ISCAS89 benchmark suites, with correlated input vector sets, resulted in a maximum compaction ratio of 65.57X (average 38.14X) and maximum power estimation error of 2.4% (average 2.06%). Since the size of the compact vector set used for simulation is smaller, the simulation time will be shorter and will significantly speed up the design cycle.
Radjassamy
R
R
Richardson VLSI Lab., Hewlett Packard, Richardson, TX, USA.
Carothers
J D
JD