title: A pulse-based, parallel-element macromodel for ferroelectric capacitors.
abstract: A pulse-based behavioral model is proposed and implemented in HSPICE. Hysteresis-loop and pulse measurement results are used to extract the model parameters. The model accurately predicts the bitline voltage of a ferroelectric memory testchip.
authors.affiliation: Department of Electrical and Computer Engineering, University of Toronto, Toronto, Ontario, Canada M5S 3G4. ali@eecg.toronto.edu
authors.forename: A
authors.initials: A
authors.lastname: Sheikholeslami
authors.forename: P G
authors.initials: PG
authors.lastname: Gulak
authors.forename: H
authors.initials: H
authors.lastname: Takauchi
authors.forename: H
authors.initials: H
authors.lastname: Tamura
authors.forename: H
authors.initials: H
authors.lastname: Yoshioka
authors.forename: T
authors.initials: T
authors.lastname: Tamura