title: Hardware implementation of CMAC neural network with reduced storage requirement.
abstract: The cerebellar model articulation controller (CMAC) neural network has the advantages of fast convergence speed and low computation complexity. However, it suffers from a low storage space utilization rate on weight memory. In this paper, we propose a direct weight address mapping approach, which can reduce the required weight memory size with a utilization rate near 100%. Based on such an address mapping approach, we developed a pipeline architecture to efficiently perform the addressing operations. The proposed direct weight address mapping approach also speeds up the computation for the generation of weight addresses. Besides, a CMAC hardware prototype used for color calibration has been implemented to confirm the proposed approach and architecture.
authors.affiliation: Dept. of Electron. Eng., Kao Yuan Jr. Coll. of Technol. and Commerce, Kaohsiung.
authors.forename: J S
authors.initials: JS
authors.lastname: Ker
authors.forename: Y H
authors.initials: YH
authors.lastname: Kuo
authors.forename: R C
authors.initials: RC
authors.lastname: Wen
authors.forename: B D
authors.initials: BD
authors.lastname: Liu