title: VLSI implementation of synaptic weighting and summing in pulse coded neural-type cells.
abstract: Presents the hardware realization for synaptic weighting and summing using pulse-coded neural-type cells (NTCs). The basic information processing element (NTC) encodes the information into the form of pulse duty cycles using voltage-controlled resistors, for which a pulse duty cycle modulation technique is proposed. Summation is executed by a simple capacitor circuit as a current integrator. Layouts and measurements on a fabricated integrated design are included.
authors.affiliation: Dept. of Electr. Eng. and Comput. Sci., George Washington Univ., DC.
authors.forename: G
authors.initials: G
authors.lastname: Moon
authors.forename: M E
authors.initials: ME
authors.lastname: Zaghloul
authors.forename: R W
authors.initials: RW
authors.lastname: Newcomb