VLSI implementation of synaptic weighting and summing in pulse coded neural-type cells.
Presents the hardware realization for synaptic weighting and summing using pulse-coded neural-type cells (NTCs). The basic information processing element (NTC) encodes the information into the form of pulse duty cycles using voltage-controlled resistors, for which a pulse duty cycle modulation technique is proposed. Summation is executed by a simple capacitor circuit as a current integrator. Layouts and measurements on a fabricated integrated design are included.
Moon
G
G
Dept. of Electr. Eng. and Comput. Sci., George Washington Univ., DC.
Zaghloul
M E
ME
Newcomb
R W
RW