title: Digital neural emulators using tree accumulation and communication structures.
abstract: Three digital artificial neural network processors suitable for the emulation of fully interconnected neural networks are proposed. The processors use N(2) multipliers and an arrangement of tree structures that provide the communication and accumulation function either individually or in a combined manner using communicating adder trees. The performance for the emulation of an N-neuron network for all processors is achieved in 2log(2)N+C time units, where C is a constant equal to the multiplication, neuron activation, and internal fixed delays. The feasibility and characteristics of the proposed configurations to emulate single and/or multiple neural networks simultaneously are discussed, and a comparison with recently proposed neurocomputer architectures is reported.
authors.affiliation: IBM Corp., Endicott, NY.
authors.forename: G G
authors.initials: GG
authors.lastname: Pechanek
authors.forename: S
authors.initials: S
authors.lastname: Vassiliadis
authors.forename: J G
authors.initials: JG
authors.lastname: Delgado-Frias