title: An analog implementation of discrete-time cellular neural networks.
abstract: An analog circuit structure for the realization of discrete-time cellular neural networks (DTCNNs) is introduced. The computation is done by a balanced clocked circuit based on the idea of conductance multipliers and operational transconductance amplifiers. The circuit is proposed for a one-neighborhood on a hexagonal grid, but can also be modified to larger neighborhoods and/or other grid topologies. A layout was designed for a standard CMOS process, and the corresponding HSPICE simulation results are given. A test chip containing 16 cells was fabricated, and measurements of the transfer characteristics are provided. The functional behavior is demonstrated for a simple example.
authors.affiliation: Tech. Univ. of Munich.
authors.forename: H
authors.initials: H
authors.lastname: Harrer
authors.forename: J A
authors.initials: JA
authors.lastname: Nossek
authors.forename: R
authors.initials: R
authors.lastname: Stelzl