title: Neural network implementation using a single MOST per synapse.
abstract: A VLSI implementation of an artificial neural network using a single n-channel MOS (metal-oxide semiconductor) transistor per synapse is investigated. The simplicity of the design is achieved by using pulse width modulation to represent neural activity and by using a novel technique to manipulate negative weights. A simple multilayer perceptron (MLP) network was simulated using the SPICE circuit simulator and the performance of a hardware realization of the same MLP network was measured. Simulations and measurements are shown to agree well.
authors.affiliation: Dept. of Electr. Eng. and Electron., Liverpool Univ.
authors.forename: D E
authors.initials: DE
authors.lastname: Johnson
authors.forename: J S
authors.initials: JS
authors.lastname: Marsland
authors.forename: W
authors.initials: W
authors.lastname: Eccleston