A four-quadrant subthreshold mode multiplier for analog neural-network applications.
A new four-quadrant CMOS analog multiplier is presented, based on devices operating in the subthreshold mode of conduction. The proposed circuit is a cross-coupled quad structure in which differential multiplication is obtained by driving the gate and bulk (back gate) terminals of the devices. Analysis and simulation have shown that the new structure has the characteristics required for the design of very large scale integration (VLSI) analog neural networks. Although operating at subthreshold current levels, reasonable speed can be obtained since voltage swings are in the range of a few V(t). The behavior of the basic multiplier has been assessed experimentally using transistor-arrays and simulation studies on a network including 11 neurons and 31 synapses indicate a useful level of functionality.
Coue
D
D
Sch. of Electron. Commun. and Electr. Eng., Plymouth Univ.
Wilson
G
G