title: Toward a general-purpose analog VLSI neural network with on-chip learning.
abstract: This paper describes elements necessary for a general-purpose low-cost very large scale integration (VLSI) neural network. By choosing a learning algorithm that is tolerant of analog nonidealities, the promise of high-density analog VLSI is realized. A 64-synapse, 8-neuron proof-of-concept chip is described. The synapse, which occupies only 4900 mum(2) in a 2-mum technology, includes a hybrid of nonvolatile and dynamic weight storage that provides fast and accurate learning as well as reliable long-term storage with no refreshing. The architecture is user-configurable in any one-hidden-layer topology. The user-interface is fully microprocessor compatible. Learning is accomplished with minimal external support; the user need only present inputs, targets, and a clock. Learning is fast and reliable. The chip solves four-bit parity in an average of 680 ms and is successful in about 96% of the trials.
authors.affiliation: Ericsson Inc., Research Triangle Park, NC.
authors.forename: A J
authors.initials: AJ
authors.lastname: Montalvo
authors.forename: R S
authors.initials: RS
authors.lastname: Gyurcsik
authors.forename: J J
authors.initials: JJ
authors.lastname: Paulos