title: A low-power VLSI arrhythmia classifier.
abstract: The design, implementation, and operation of a low-power multilayer perceptron chip (Kakadu) in the framework of a cardiac arrhythmia classification system is presented in this paper. This classifier, called MATIC, makes timing decisions using a decision tree, and a neural network is used to identify heartbeats with abnormal morphologies. This classifier was designed to be suitable for use in implantable devices and a VLSI (very large scale integration) neural-network chip (Kakadu) was designed so that the computationally expensive neural-network algorithm can be implemented with low power consumption. Kakadu implements a (10,6,4) perceptron and has a typical power consumption of tens of microwatts. When used with the arrhythmia classification system, the chip can operate with an average power consumption of less than 25 nW.
authors.affiliation: Dept. of Electr. Eng., Sydney Univ., NSW.
authors.forename: P W
authors.initials: PW
authors.lastname: Leong
authors.forename: M A
authors.initials: MA
authors.lastname: Jabri