title: Key integration technologies for nanoscale FRAMs.
abstract: We discuss key technologies of 180-nm node ferroelectric memories, whose process integration is becoming extremely complex when device dimension shrinks into a nano scale. This is because process technology in ferroelectric integration does not extend to conventional shrink technology due to many difficulties of coping with metal-insulator-metal (MIM) capacitors. The key integration technologies in ferroelectric random access memory (FRAM) comprise: etching technology to have less plasma damage; stack technology for the preparation of robust ferroelectrics; capping technology to encapsulate cell capacitors; and vertical conjunction technology to connect cell capacitors to the plate line. What has been achieved from these novel approaches is not only to have a peak-to-peak value of 675 mV in bit-line potential but also to ensure a sensing margin of 300 mV in opposite-state retention, even after 1000 hour suffering at 150 degrees C.
authors.affiliation: Advanced Technology Development Team 2, Semiconductor R and D Center, Samsung Electronics Company Ltd., Yongin-City, Gyunggi-Do, Korea. djjung@samsung.com
authors.forename: Dong J
authors.initials: DJ
authors.lastname: Jung
authors.forename: Hyun-Ho
authors.initials: HH
authors.lastname: Kim
authors.forename: Kinam
authors.initials: K
authors.lastname: Kim
mesh_terms: D016248:Computer Storage Devices; D004867:Equipment Design; D019544:Equipment Failure Analysis; D016247:Information Storage and Retrieval / Q000379:methods*; D036103:Nanotechnology / Q000295:instrumentation* / Q000379:methods; D012815:Signal Processing, Computer-Assisted / Q000295:instrumentation*; D018511:Systems Integration