Learning in linear systolic neural network engines: analysis and implementation.
Linear systolic processor arrays are a widely proposed digital architecture for neural networks. This paper reports the analysis of a range of training algorithms implemented on a linear systolic ring, with a view to (a) identifying low-level instruction requirements, (b) assessing different hardware structures for PE implementation and (c) evaluating the impact of different array controller designs. Quantitative data is derived and used to determine cost-effective PE and controller hardware constructs.
Jones
S R
SR
Dept. of Electron. and Electr. Eng., Loughborough Univ. of Technol.
Sammut
K M
KM
Hunter
J
J