Spatial control of quantum sized nanocrystal arrays onto silicon wafers.
Monolayer arrays of monodispersed nanocrystals (<10 nm) onto three dimensional (3D) substrates have considerable potential for various engineering applications such as highly integrated memory devices, solar cells, biosensors and photo and electro luminescent displays because of their highly integrated features with nanocrystal homogeneity. However, most reports on nanocrystal arrays have focused on two dimensional (2D) flat substrates, and the production of wafer-scale monolayer arrays is still challenging. Here we address the feasibility of arraying nanocrystal monolayers in wafer-scale onto 3D substrates. We present both metal (Pd) and semiconductor (CdSe) nanocrystals arrayed in monolayer onto trenched silicon wafers (4 inch diameter) using a facile electrostatic adsorption scheme. In particular, CdSe nanocrystal arrays in the trench well showed superior luminescent efficiency compared to those onto the protruded trench flat, due to the densely arrayed CdSe nanocrystals in the vertical direction. Furthermore, the surface coverage controllability was investigated using a 2D silicon substrate. Our approach can be applied to generate highly efficient displays, memory chips and integrated sensing devices.
Choi
Seong Jae
SJ
Samsung Advanced Institute of Technology, Mt. 14-1, Giheung-Gu Yongin-Si, Gyeonggi-Do, 449-712 Korea.
Yi
Dong Kee
DK
Choi
Jae-Young
JY
Park
Jong-Bong
JB
Song
In-Yong
IY
Jang
Eunjoo
E
Lee
Joo In
JI
An
Minshi
M
Hong
Jong-Dal
JD
Yoon
Seon-Mi
SM
Shin
Hyeon-Jin
HJ