title: Demonstration and architectural analysis of complementary metal-oxide semiconductor /multiple-quantum-well smart-pixel array cellular logic processors for single-instruction multiple-data parallel-pipeline processing.
abstract: We present an optoelectronic-VLSI system that integrates complementary metal-oxide semiconductor/multiple-quantum-well smart pixels for high-throughput computation and signal processing. The system uses 5 x 10 cellular smart-pixel arrays with intrachip electrical mesh interconnections and interchip optical point-to-point interconnections. Each smart pixel is a fine grain microprocessor that executes binary image algebra instructions. There is one dual-rail optical modulator output and one dual-rail optical detector input in each pixel. These optical input-output arrays provide chip-to-chip optical interconnects. Cascading these smart-pixel array chips permits direct transfer of two-dimensional data or images in parallel. We present laboratory demonstrations of the system for digital image edge detection and digital video motion estimation. We also analyze the performance of the system compared with that of conventional single-instruction-multiple-data processors.
authors.affiliation: Signal and Image Processing Institute, Department of Electrical Engineering, University of Southern California, Los Angeles, California 90089-2564, USA.
authors.forename: J M
authors.initials: JM
authors.lastname: Wu
authors.forename: C B
authors.initials: CB
authors.lastname: Kuznia
authors.forename: B
authors.initials: B
authors.lastname: Hoanca
authors.forename: C H
authors.initials: CH
authors.lastname: Chen
authors.forename: A A
authors.initials: AA
authors.lastname: Sawchuk