All-optical 100-Gbit/s word packet time-division-multiplexed access node in a looped-back configuration: enabling technologies for sequential add-drop functionality.
We experimentally demonstrate the adding, dropping, and passing through of 100-Gbit/s word packets in a looped-back all-optical time-division-multiplexed (TDM) access node. Packets are routed with a 17-dB contrast ratio and demultiplexed with a 20-dB contrast ratio. This node uses short 100-Gbit/s words to demonstrate its potential to process data packets from multiple sources and to perform packet switching in a multinode ring network configuration. The ability to tolerate timing jitter as well as varying input signal characteristics is essential to an all-optical access node in a multinode network. For 2-ps input pulses, the header processor has a timing window of approximately 5 ps, and the demultiplexer has a timing window of approximately 5.5 ps. This allows for tolerance to bit-to-bit timing jitters or to an increase in the pulse width of as much as 3 ps. Packet-to-packet timing jitter is detected and compensated by the technique used to synchronize the local source to each packet. The key enabling technologies of an all-optical TDM packet add-drop multiplexer are discussed, including an erbium-doped fiber laser, a nonlinear optical loop mirror logic gate, self-synchronization to incoming packets with a fast-saturation/slow-recovery gain element followed by an intensity discriminator, a two-wavelength nonlinear optical loop mirror demultiplexer, and synchronization of new packets to the network packet rate with a phase-locked loop. The local source is automatically synchronized to the incoming packet, because it uses an extracted pulse from the packet, which has a contrast ratio of >20 dB to the rest of the packet. Finally, new packets are added by use of a local laser and a synchronization method, which gives a timing jitter of approximately 1 ps. Using a statistical method of measuring Q value with picosecond resolution, we show that a header processor with two cascaded logic gates has a Q value of 7.1 with a 95% confidence level.
Lou
J W
JW
Department of Electrical Engineering and Computer Science, University of Michigan, 1301 Beal Avenue, Ann Arbor, Michigan 48109-2122, USA. jwlou@engin.umich.edu
Liang
Y
Y
Boyraz
O
O
Islam
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MN