Compatibility assessment of CVD growth of carbon nanofibers on bulk CMOS devices.
We compare the level of deterioration in the basic functionality of individual transistors on ASIC chips fabricated in standard 130 nm bulk CMOS technology when subjected to three disparate CVD techniques with relatively low processing temperature to grow carbon nanostructures. We report that the growth technique with the lowest temperature has the least impact on the transistor behavior.
Ghavanini
Farzan A
FA
Department of Microtechnology and Nanoscience, BioNano Systems Laboratory, Chalmers University of Technology, Göteborg, Sweden. Farzan@chalmers.se
Le Poche
Hélène
H
Berg
Jonas
J
Saleem
Amin M
AM
Kabir
Mohammad S
MS
Lundgren
Per
P
Enoksson
Peter
P
D002244:Carbon / Q000737:chemistry*; D002623:Chemistry Techniques, Analytical / Q000295:instrumentation* / Q000379:methods*; D008855:Microscopy, Electron, Scanning; D049329:Nanostructures / Q000737:chemistry* / Q000648:ultrastructure; D014835:Volatilization
D002244:Carbon