title: Compatibility assessment of CVD growth of carbon nanofibers on bulk CMOS devices.
abstract: We compare the level of deterioration in the basic functionality of individual transistors on ASIC chips fabricated in standard 130 nm bulk CMOS technology when subjected to three disparate CVD techniques with relatively low processing temperature to grow carbon nanostructures. We report that the growth technique with the lowest temperature has the least impact on the transistor behavior.
authors.affiliation: Department of Microtechnology and Nanoscience, BioNano Systems Laboratory, Chalmers University of Technology, Göteborg, Sweden. Farzan@chalmers.se
authors.forename: Farzan A
authors.initials: FA
authors.lastname: Ghavanini
authors.forename: Hélène
authors.initials: H
authors.lastname: Le Poche
authors.forename: Jonas
authors.initials: J
authors.lastname: Berg
authors.forename: Amin M
authors.initials: AM
authors.lastname: Saleem
authors.forename: Mohammad S
authors.initials: MS
authors.lastname: Kabir
authors.forename: Per
authors.initials: P
authors.lastname: Lundgren
authors.forename: Peter
authors.initials: P
authors.lastname: Enoksson
mesh_terms: D002244:Carbon / Q000737:chemistry*; D002623:Chemistry Techniques, Analytical / Q000295:instrumentation* / Q000379:methods*; D008855:Microscopy, Electron, Scanning; D049329:Nanostructures / Q000737:chemistry* / Q000648:ultrastructure; D014835:Volatilization
chemical_list: D002244:Carbon