Downscaling of self-aligned, all-printed polymer thin-film transistors.
Printing is an emerging approach for low-cost, large-area manufacturing of electronic circuits, but it has the disadvantages of poor resolution, large overlap capacitances, and film thickness limitations, resulting in slow circuit speeds and high operating voltages. Here, we demonstrate a self-aligned printing approach that allows downscaling of printed organic thin-film transistors to channel lengths of 100-400 nm. The use of a crosslinkable polymer gate dielectric with 30-50 nm thickness ensures that basic scaling requirements are fulfilled and that operating voltages are below 5 V. The device architecture minimizes contact resistance effects, enabling clean scaling of transistor current with channel length. A self-aligned gate configuration minimizes parasitic overlap capacitance to values as low as 0.2-0.6 pF mm(-1), and allows transition frequencies of fT = 1.6 MHz to be reached. Our self-aligned process provides a way to improve the performance of printed organic transistor circuits by downscaling, while remaining compatible with the requirements of large-area, flexible electronics manufacturing.
Noh
Yong-Young
YY
Cavendish Laboratory, University of Cambridge, JJ Thomson Avenue, Cambridge CB3 0HE, UK.
Zhao
Ni
N
Caironi
Mario
M
Sirringhaus
Henning
H
D004867:Equipment Design; D019544:Equipment Failure Analysis; D008567:Membranes, Artificial; D036103:Nanotechnology / Q000295:instrumentation*; D014173:Transistors, Electronic
D008567:Membranes, Artificial