title: Neural cache: a low-power online digital spike-sorting architecture.
abstract: Transmitting large amounts of data sensed by multi-electrode array devices is widely considered to be a challenging problem in designing implantable neural recording systems. Spike sorting is an important step to reducing the data bandwidth before wireless data transmission. The feasibility of spike sorting algorithms in scaled CMOS technologies, which typically operate on low frequency neural spikes, is determined largely by its power consumption, a dominant portion of which is leakage power. Our goal is to explore energy saving architectures for online spike sorting without sacrificing performance. In the face of non-stationary neural data, training is not always a feasible option. We present a low-power architecture for real-time online spike sorting that does not require any training period and has the capability to quickly respond to the changing spike shapes.
authors.affiliation: Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL 32611, USA.
authors.forename: Chung-Ching
authors.initials: CC
authors.lastname: Peng
authors.forename: Pawan
authors.initials: P
authors.lastname: Sabharwal
authors.forename: Rizwan
authors.initials: R
authors.lastname: Bashirullah
mesh_terms: D000200:Action Potentials / Q000502:physiology*; D000465:Algorithms; D001921:Brain / Q000502:physiology; D016000:Cluster Analysis; D011211:Electric Power Supplies; D006801:Humans; D008959:Models, Neurological; D019736:Prostheses and Implants; D012815:Signal Processing, Computer-Assisted / Q000295:instrumentation*