title: Impact of Single pMOSFET Dielectric Degradation on NAND Circuit Performance.
abstract: Degradation of CMOS NAND logic circuits resulting from dielectric degradation of a single pMOSFET using constant voltage stress has been examined by means of a switch matrix technique. As a result, the NAND gate rise time increases by greater than 65%, which may lead to timing errors in high frequency digital circuits. In addition, the NAND gate DC switching point voltage shifts by nearly 11% which may be of consequence for analog or mixed signal applications. Experimental results for the degraded pMOSFET reveal a decrease in drive current by approximately 43%. There is also an increase in threshold voltage by 23%, a decrease in source to drain conductance of 30%, and an increase in channel resistance of about 44%. A linear relationship between the degradation of the pMOSFET channel resistance and the increase in NAND gate rise time is demonstrated, thereby providing experimental evidence of the impact of a single degraded pMOSFET on NAND circuit performance.
authors.affiliation: Boise State University, Electrical and Computer Engineering Department, 1910 University Dr., Boise, ID 83725, USA.
authors.forename: D
authors.initials: D
authors.lastname: Estrada
authors.forename: M L
authors.initials: ML
authors.lastname: Ogas
authors.forename: R G
authors.initials: RG
authors.lastname: Southwick
authors.forename: P M
authors.initials: PM
authors.lastname: Price
authors.forename: R J
authors.initials: RJ
authors.lastname: Baker
authors.forename: W B
authors.initials: WB
authors.lastname: Knowlton