Low-power, transparent optical network interface for high bandwidth off-chip interconnects.
The recent emergence of multicore architectures and chip multiprocessors (CMPs) has accelerated the bandwidth requirements in high-performance processors for both on-chip and off-chip interconnects. For next generation computing clusters, the delivery of scalable power efficient off-chip communications to each compute node has emerged as a key bottleneck to realizing the full computational performance of these systems. The power dissipation is dominated by the off-chip interface and the necessity to drive high-speed signals over long distances. We present a scalable photonic network interface approach that fully exploits the bandwidth capacity offered by optical interconnects while offering significant power savings over traditional E/O and O/E approaches. The power-efficient interface optically aggregates electronic serial data streams into a multiple WDM channel packet structure at time-of-flight latencies. We demonstrate a scalable optical network interface with 70% improvement in power efficiency for a complete end-to-end PCI Express data transfer.
Department of Electrical Engineering, Columbia University, 500 West 120th Street, New York, NY 10027, USA.
Odile
O
Liboiron-Ladouceur
Howard
H
Wang
Ajay S
AS
Garg
Keren
K
Bergman
D003195:Computer Communication Networks / Q000295:instrumentation*; D017076:Computer-Aided Design; D004735:Energy Transfer; D004867:Equipment Design; D019544:Equipment Failure Analysis; D055096:Optical Devices; D055100:Optical Fibers; D015203:Reproducibility of Results; D012680:Sensitivity and Specificity; D012815:Signal Processing, Computer-Assisted / Q000295:instrumentation*; D013685:Telecommunications / Q000295:instrumentation*