Top-gated silicon nanowire transistors in a single fabrication step.
Top-gated silicon nanowire transistors are fabricated by preparing all terminals (source, drain, and gate) on top of the nanowire in a single step via dose-modulated e-beam lithography. This outperforms other time-consuming approaches requiring alignment of multiple patterns, where alignment tolerances impose a limit on device scaling. We use as gate dielectric the 10-15 nm SiO(2) shell naturally formed during vapor-transport growth of Si nanowires, so the wires can be implemented into devices after synthesis without additional processing. This natural oxide shell has negligible leakage over the operating range. Our single-step patterning is a most practical route for realization of short-channel nanowire transistors and can be applied to a number of nanodevice geometries requiring nonequivalent electrodes.
Nokia Research Centre Cambridge U.K., c/o Nanoscience Centre, University of Cambridge, Cambridge, United Kingdom. alan.colli@nokia.com
Alan
A
Colli
Abbes
A
Tahraoui
Andrea
A
Fasoli
Jani M
JM
Kivioja
William I
WI
Milne
Andrea C
AC
Ferrari