A novel method for fabricating sub-16 nm footprint T-gate nanoimprint molds.
A novel method for fabricating nanoimprint lithography (NIL) molds for T-shaped gates (T-gates) for high speed transistors is proposed and demonstrated. This method uses NIL, low pressure chemical vapor deposition and reactive ion etching processes, and avoids costly electron beam lithography and high accuracy alignment technology. Using the T-gate nanoimprint molds fabricated by this novel method, T-gates with a footprint as small as sub-16 nm were achieved. This method can be extended to fabricate a broad range of 3D nanostructures.
Peng
Can
C
NanoStructure Laboratory, Electrical Engineering Department, Princeton University, Princeton, NJ 08544, USA.
Liang
Xiaogan
X
Chou
Stephen Y
SY
D003460:Crystallization / Q000379:methods*; D004867:Equipment Design; D019544:Equipment Failure Analysis; D046911:Macromolecular Substances / Q000737:chemistry; D008422:Materials Testing; D008968:Molecular Conformation; D049329:Nanostructures / Q000737:chemistry* / Q000648:ultrastructure*; D036103:Nanotechnology / Q000295:instrumentation*; D010316:Particle Size; D012815:Signal Processing, Computer-Assisted / Q000295:instrumentation*; D013499:Surface Properties; D014173:Transistors, Electronic
D046911:Macromolecular Substances