title: Enabling cutting-edge semiconductor simulation through grid technology.
abstract: The progressive scaling of complementary metal oxide semiconductor (CMOS) transistors drives the success of the global semiconductor industry. Detailed knowledge of transistor behaviour is necessary to overcome the many fundamental challenges faced by chip and systems designers. Grid technology has enabled the unavoidable statistical variations introduced by scaling to be examined in unprecedented detail. Over 200 000 transistors have been simulated, the results of which provide detailed insight into underlying physical processes. This paper outlines recent scientific results of the nanoCMOS project and describes the way in which the scientific goals have been reflected in the grid-based e-Infrastructure.
authors.affiliation: Device Modelling Group, University of Glasgow, Glasgow G12 8QQ, UK. d.reid@elec.gla.ac.uk
authors.forename: Dave
authors.initials: D
authors.lastname: Reid
authors.forename: Campbell
authors.initials: C
authors.lastname: Millar
authors.forename: Scott
authors.initials: S
authors.lastname: Roy
authors.forename: Gareth
authors.initials: G
authors.lastname: Roy
authors.forename: Richard
authors.initials: R
authors.lastname: Sinnott
authors.forename: Gordon
authors.initials: G
authors.lastname: Stewart
authors.forename: Graeme
authors.initials: G
authors.lastname: Stewart
authors.forename: Asen
authors.initials: A
authors.lastname: Asenov