title: Single-PPLN-based simultaneous half-adder, half-subtracter, and OR logic gate: proposal and simulation.
abstract: We propose and simulate all-optical simultaneous half-adder, half-subtracter, and OR logic gate at 40 Gbit/s based on the cascaded sum-and difference-frequency generation (SFG+DFG) using only one periodically poled lithium niobate (PPLN) waveguide. The SFG and DFG processes generate the Borrow and Carry outputs, respectively. The Sum/Difference and OR are obtained by properly combining the outputs from PPLN after SFG+DFG. The eye diagrams, pulse width, quality-factor (Q-factor), extinction ratio (ER), and tunability are calculated and discussed, showing impressive operation performance.
authors.forename: Jian
authors.initials: J
authors.lastname: Wang
authors.forename: Junqiang
authors.initials: J
authors.lastname: Sun
authors.forename: Qizhen
authors.initials: Q
authors.lastname: Sun