Highly aligned scalable platinum-decorated single-wall carbon nanotube arrays for nanoscale electrical interconnects.
We present the fabrication and characterization of nanoscale electrical interconnect test structures constructed from aligned single-wall carbon nanotubes using a template-based fluidic assembly process. This CMOS-friendly process enables the formation of highly aligned parallel nanotube interconnect structures on SiO(2)/Si substrates of widths and lengths that are limited only by lithographical limits and, hence, can be easily integrated onto existing Si-based platforms. These structures can withstand current densities of approximately 10(7) A.cm(-2), comparable or better than copper at similar dimensions. Both the nanotube alignment and failure current density improve with decreasing structure width. In addition, we present a novel Pt nanocluster decoration method that drastically decreases the resistivity of the test structures. Ab initio density functional theory calculations indicate that the increase in conductivity of the nanotubes is caused by an increase in conduction channels close to their Fermi levels due to the platinum nanocluster decoration, with a possible conversion of the semiconducting single-wall carbon nanotubes into metallic ones. These results reflect a huge step toward the proposed replacement of copper-based interconnects with carbon nanotubes at gigascale integration levels.
Kim
Young Lae
YL
Department of Electrical & Computer Engineering, Northeastern University, Boston, MA 02115, USA.
Li
Bo
B
An
Xiaohong
X
Hahm
Myung Gwan
MG
Chen
Li
L
Washington
Morris
M
Ajayan
P M
PM
Nayak
Saroj K
SK
Busnaina
Ahmed
A
Kar
Swastik
S
Jung
Yung Joon
YJ