title: Architectural and performance considerations for a 10(7)-instruction/sec optoelectronic central processing unit.
abstract: Architectural considerations for a multiple-instruction, single-data-based optoelectronic central processing unit operating at 10(7) instructions per second are detailed. Central to the operation of this device is a giant fiber-optic content-addressable memory in a programmable logic array configuration. The design includes four instructions and emphasizes the fan-in and fan-out capabilities of optical systems. Interconnection limitations and scaling issues are examined.
authors.forename: R
authors.initials: R
authors.lastname: Arrathoon
authors.forename: S
authors.initials: S
authors.lastname: Kozaitis