The large-scale integration of high-performance silicon nanowire field effect transistors.
In this work we present a CMOS-compatible self-aligning process for the large-scale-integration of high-performance nanowire field effect transistors with well-saturated drain currents, steep subthreshold slopes at low drain voltage and a large on/off current ratio (>10(7)). The subthreshold swing is as small as 45 mV/dec, which is substantially beyond the thermodynamic limit (60 mV/dec) of conventional planar MOSFETs. These excellent device characteristics are achieved by using a clean integration process and a device structure that allows effective gate-channel-source coupling to tune the source/drain Schottky barriers at the nanoscale.
Li
Qiliang
Q
Department of Electrical and Computer Engineering, George Mason University, Fairfax, VA 22030, USA. qli6@gmu.edu
Zhu
Xiaoxiao
X
Yang
Yang
Y
Ioannou
Dimitris E
DE
Xiong
Hao D
HD
Kwon
Doo-Won
DW
Suehle
John S
JS
Richter
Curt A
CA
D036103:Nanotechnology / Q000295:instrumentation* / Q000379:methods*; D053770:Nanowires / Q000737:chemistry*; D012825:Silicon / Q000737:chemistry*; D014173:Transistors, Electronic
D012825:Silicon