title: The large-scale integration of high-performance silicon nanowire field effect transistors.
abstract: In this work we present a CMOS-compatible self-aligning process for the large-scale-integration of high-performance nanowire field effect transistors with well-saturated drain currents, steep subthreshold slopes at low drain voltage and a large on/off current ratio (>10(7)). The subthreshold swing is as small as 45 mV/dec, which is substantially beyond the thermodynamic limit (60 mV/dec) of conventional planar MOSFETs. These excellent device characteristics are achieved by using a clean integration process and a device structure that allows effective gate-channel-source coupling to tune the source/drain Schottky barriers at the nanoscale.
authors.affiliation: Department of Electrical and Computer Engineering, George Mason University, Fairfax, VA 22030, USA. qli6@gmu.edu
authors.forename: Qiliang
authors.initials: Q
authors.lastname: Li
authors.forename: Xiaoxiao
authors.initials: X
authors.lastname: Zhu
authors.forename: Yang
authors.initials: Y
authors.lastname: Yang
authors.forename: Dimitris E
authors.initials: DE
authors.lastname: Ioannou
authors.forename: Hao D
authors.initials: HD
authors.lastname: Xiong
authors.forename: Doo-Won
authors.initials: DW
authors.lastname: Kwon
authors.forename: John S
authors.initials: JS
authors.lastname: Suehle
authors.forename: Curt A
authors.initials: CA
authors.lastname: Richter
mesh_terms: D036103:Nanotechnology / Q000295:instrumentation* / Q000379:methods*; D053770:Nanowires / Q000737:chemistry*; D012825:Silicon / Q000737:chemistry*; D014173:Transistors, Electronic
chemical_list: D012825:Silicon