A low-power area-efficient 8 bit SAR ADC using dual capacitor arrays for neural microsystems.
We report an area-efficient 8bit SAR ADC using dual capacitor array banks for brain signal interface microsystems. The proposed ADC consumes 680nW and the total chip area is 0.035 mm(2). We reduced the area and power by a factor of eight when compared with conventional approaches. If we increase the resolution, the area and power reduction factor exponentially increases in our architecture (e.g., a factor of 16 for 10 bit resolution). The measured SNDR, SFDR, THD, and ENOB are 42.82 +/- 0.47 dB, 57.90 +/- 2.82dB, -53.58 +/- 2.15 dB, and 6.65 +/- 0.07 bits, respectively.
Chang
Sun-Il
SI
Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI 48109 USA. schang@umich.edu
Yoon
Euisik
E
D009474:Neurons / Q000502:physiology*; D012815:Signal Processing, Computer-Assisted