title: VLSI architecture of NEO spike detection with noise shaping filter and feature extraction using informative samples.
abstract: An emerging class of multi-channel neural recording systems aims to simultaneously monitor the activity of many neurons by miniaturizing and increasing the number of recording channels. Vast volume of data from the recording systems, however, presents a challenge for processing and transmitting wirelessly. An on-chip neural signal processor is needed for filtering uninterested recording samples and performing spike sorting. This paper presents a VLSI architecture of a neural signal processor that can reliably detect spike via a nonlinear energy operator, enhance spike signal over noise ratio by a noise shaping filter, and select meaningful recording samples for clustering by using informative samples. The architecture is implemented in 90-nm CMOS process, occupies 0.2 mm(2), and consumes 0.5 mW of power.
authors: School of Engineering, University of California, Santa Cruz, CA 95064, USA. linh@soe.ucsc.edu
authors: Linh
authors: L
authors: Hoang
authors: Zhi
authors: Z
authors: Yang
authors: Wentai
authors: W
authors: Liu
mesh_terms: D000200:Action Potentials / Q000502:physiology*; D000465:Algorithms; D001185:Artificial Intelligence; D017076:Computer-Aided Design; D004867:Equipment Design; D019544:Equipment Failure Analysis; D006801:Humans; D009474:Neurons / Q000502:physiology*; D010363:Pattern Recognition, Automated / Q000379:methods*; D015203:Reproducibility of Results; D012680:Sensitivity and Specificity; D012815:Signal Processing, Computer-Assisted / Q000295:instrumentation*