A preferential design approach for energy-efficient and robust implantable neural signal processing hardware.
For implantable neural interface applications, it is important to compress data and analyze spike patterns across multiple channels in real time. Such a computational task for online neural data processing requires an innovative circuit-architecture level design approach for low-power, robust and area-efficient hardware implementation. Conventional microprocessor or Digital Signal Processing (DSP) chips would dissipate too much power and are too large in size for an implantable system. In this paper, we propose a novel hardware design approach, referred to as "Preferential Design" that exploits the nature of the neural signal processing algorithm to achieve a low-voltage, robust and area-efficient implementation using nanoscale process technology. The basic idea is to isolate the critical components with respect to system performance and design them more conservatively compared to the noncritical ones. This allows aggressive voltage scaling for low power operation while ensuring robustness and area efficiency. We have applied the proposed approach to a neural signal processing algorithm using the Discrete Wavelet Transform (DWT) and observed significant improvement in power and robustness over conventional design.
Narasimhan
Seetharam
S
Department of Electrical Engineering and Computer Science, Case Western Reserve University, Cleveland, OH 44106, USA. sxn124@case.edu
Chiel
Hillel J
HJ
Bhunia
Swarup
S
D000200:Action Potentials / Q000502:physiology*; D000465:Algorithms; D011211:Electric Power Supplies; D004558:Electric Stimulation / Q000295:instrumentation*; D004735:Energy Transfer; D004867:Equipment Design; D019544:Equipment Failure Analysis; D009474:Neurons / Q000502:physiology*; D019736:Prostheses and Implants; D015203:Reproducibility of Results; D012680:Sensitivity and Specificity; D012815:Signal Processing, Computer-Assisted / Q000295:instrumentation*