title: Adaptive resolution ADC array for neural implant.
abstract: This paper describes an ADC array for an implantable prosthetic processor which digitizes neural signals sensed by a microelectrode array. The ADC array consists of 96 variable resolution ADC base cells. The base ADC has been implemented in 0.13 microm CMOS as a 100kS/s SAR ADC whose resolution can be varied from 3 to 8-bits with corresponding power consumption of 0.23 microW to 0.90 microW achieving an ENOB of 7.8 at the 8-bit setting. The resolution of each ADC cell in the array is varied according to neural data content of the signal from the corresponding electrode. Resolution adaptation reduces power consumption by a factor of 2.3 whilst maintaining an effective 7.8-bit resolution across all channels.
authors: Department of Electrical Engineering, Stanford University, Stanford, CA 94305, USA.
authors: Stephen
authors: S
authors: O'Driscoll
authors: Teresa H
authors: TH
authors: Meng
mesh_terms: D000703:Analog-Digital Conversion; D001921:Brain / Q000502:physiology*; D004569:Electroencephalography / Q000295:instrumentation*; D004867:Equipment Design; D019544:Equipment Failure Analysis; D019736:Prostheses and Implants; D015203:Reproducibility of Results; D012680:Sensitivity and Specificity; D012815:Signal Processing, Computer-Assisted / Q000295:instrumentation*; D013686:Telemetry / Q000295:instrumentation*