Low operating bias and matched input-output characteristics in graphene logic inverters.
We developed a simple and novel method to fabricate complementary-like logic inverters based on ambipolar graphene field-effect transistors (FETs). We found that the top gate stacks (with both the metal and oxide layers) can be simply prepared with only one-step deposition process and show high capacitive efficiency. By employing such a top gate as the operating terminal, the operating bias can be lowered within 2 V. In addition, the complementary p- and n-type FET pairs can be also simply fulfilled through potential superposition effect from the drain bias. The inverters can be operated, with up to 4-7 voltage gains, in both the first and third quadrants due to the ambipolarity of graphene FETs. For the first time, a match between the input and output voltages is achieved in graphene logic devices, indicating the potential in direct cascading of multiple devices for future nanoelectronic applications.
International Center for Materials Nanoarchitectonics (MANA), National Institute for Materials Science, Tsukuba, Ibaraki, Japan.
Song-Lin
SL
Li
Hisao
H
Miyazaki
Akichika
A
Kumatani
Akinobu
A
Kanda
Kazuhito
K
Tsukagoshi