title: Butterfly interconnection network: design of multiplier, flip-flop, and shift register.
abstract: A 2 × 2 bit multiplier is designed by the use of a butterfly interconnection network. The butterfly topology is also used to design a sequential flip-flop and a multibit parallel-in parallel-out shift register.
authors.forename: K M
authors.initials: KM
authors.lastname: Iftekharuddin
authors.forename: M A
authors.initials: MA
authors.lastname: Karim