title: A low-power self-biased neural amplifier for implantable EEG recording system ICs.
abstract: This paper presents a low-power and self-biased neural amplifier for implantable EEG recording system ICs with a high-density interface. To achieve low-power consumption, small die-area, high gain, and high CMRR, a fully differential Chappell OTA is employed along with a capacitive feedback loop. The amplifier operating at ± 1.2V has a gain of 65.6dB and consumes a power of 1.7 microW. The bandwidth extends from a low-frequency cutoff of below 1 Hz to a high-frequency cutoff of 300Hz which is suitable for EEG signals. This proposed amplifier has an input-referred noise of 9.76 mmicroV(RMS) and THD of 1.86% with respect to 1mV(PP) input at 100Hz. This low-power self-biased neural amplifier occupies an active die-area of 0.244 mm(2) and is under fabrication in 0.35 microm CMOS 4M2P Process.
authors.affiliation: Department of Electrical Engineering, University of California at Santa Cruz, CA 95064, USA. jungsuk@soe.ucsc.edu
authors.forename: Jungsuk
authors.initials: J
authors.lastname: Kim
authors.forename: Kenneth
authors.initials: K
authors.lastname: Pedrotti
mesh_terms: D000669:Amplifiers, Electronic; D011211:Electric Power Supplies; D004569:Electroencephalography / Q000295:instrumentation*; D004867:Equipment Design; D019544:Equipment Failure Analysis; D016247:Information Storage and Retrieval; D019736:Prostheses and Implants; D012815:Signal Processing, Computer-Assisted / Q000295:instrumentation*