title: Reconfigurable embedded system architecture for next-generation Neural Signal Processing.
abstract: This work presents a new architectural framework for next generation Neural Signal Processing (NSP). The essential features of the NSP hardware platform include scalability, reconfigurability, real-time processing ability and data storage. This proposed framework has been implemented in a proof-of-concept NSP prototype using an embedded system architecture synthesized in a Xilinx(®)Virtex(®)5 development board. The prototype includes a threshold-based spike detector and a fuzzy logic-based spike sorter.
authors.affiliation: Neural Instrumentation Lab, Temple University, Philadelphia, PA 19122, USA. bkintex@temple.edu
authors.forename: Karthikeyan
authors.initials: K
authors.lastname: Balasubramanian
authors.forename: Iyad
authors.initials: I
authors.lastname: Obeid
mesh_terms: D000200:Action Potentials / Q000502:physiology*; D000818:Animals; D003205:Computing Methodologies; D004569:Electroencephalography / Q000295:instrumentation*; D004867:Equipment Design; D019544:Equipment Failure Analysis; D006801:Humans; D009474:Neurons / Q000502:physiology*; D012815:Signal Processing, Computer-Assisted / Q000295:instrumentation*