A new cost effective method of planarisation for multiple metal layers in the sub-100 nm-region.
The availability of multiple metal layers has become essential for high-density layouts and economic chip size. The presented paper describes an efficient and low-cost alternative to Chemical-Mechanical-Polishing (CMP). The method uses an auxiliary wafer as a sort of plunger. Starting with a preprocessed wafer, for example from a Complementary-Metal-Oxide-Semiconductor (CMOS) technology, a spin-on glass is applied before the deposition of the first metal layer. Afterwards a second silicon wafer will be covered homogeneously with photo resist and subsequentially coated with aluminum or titanium. This wafer serves as a plunger, while the metal layer protects the photo resist against impression. Whilst the plunger is pressed down on the spin-on glass, the first wafer is cooled down bonding the two wafers together. Separation of the wafers is accomplished by removing the photo resist layer. After the separation step any remaining photo resist as well as the aluminum layer are removed by etching. This process results in a planar surface which is optimally suited for the deposition and structuring of further metal layers which lead to more freedom concerning the complex interconnects in modern analog and digital circuits.
Intelligent Microsystems Institute, Faculty of Electrical Engineering, TU Dortmund Emil-Figge-Str. 68, D-44227 Dortmund, Germany.
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Poloczek
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Keller
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Kallis
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Fiedler