title: Variations in the memory capability of nonvolatile memory devices fabricated using hybrid composites of InP nanoparticles and a polystyrene layer due to the scale-down.
abstract: InP nanoparticles were formed using a solution method, and the InP nanoparticles that were embedded in a polystyrene (PS) layer were formed using the spin-coating method. The transmission electron microscopy images showed that the InP nanoparticles were randomly distributed in the PS layer. The measured capacitance-voltage (C-V) of the Al/InP nanoparticles embedded in the PS layer/PS/p-Si(100) device at 300 K showed a clockwise hysteresis of the C-V curve. Based on the C-V results, the origin of variations in the memory storage of nonvolatile memory devices that were fabricated using InP nanoparticles embedded in a PS layer due to the scale-down was described.
authors: Department of Electronics and Computer Engineering, Hanyang University, Seoul 133-791, Korea.
authors: S H
authors: SH
authors: Lee
authors: D Y
authors: DY
authors: Yun
authors: J H
authors: JH
authors: Jung
authors: J H
authors: JH
authors: You
authors: T W
authors: TW
authors: Kim
authors: E
authors: E
authors: Ryu
authors: S W
authors: SW
authors: Kim