title: Sub-30 nm gate template fabrication for nanoimprint lithography using spacer patterning technology.
abstract: In this study, we present a spacer patterning technology for sub-30 nm gate template which is used for nano-scale MOSFETs fabrication. A spacer patterning technology using a poly-silicon micro-feature and a chemical vapor deposition (CVD) SiO2 spacer has been developed, and the sub-30 nm structures by conventional dry etching and chemical mechanical polishing are demonstrated. The minimum-sized features are defined not by the photolithography but by the CVD film thickness. Therefore, this technology yields a large-area template with critical dimension of minimum-sized features much smaller than that achieved by optical lithography.
authors: RFID/USN Research Department, Electronics and Telecommunications Research Institute, 138 Gajeongno, Yuseong-gu, Daejeon 305-700, Korea.
authors: Kun-Sik
authors: KS
authors: Park
authors: Kyu-Ha
authors: KH
authors: Baik
authors: Dong-Pyo
authors: DP
authors: Kim
authors: Jong-Chang
authors: JC
authors: Woo
authors: Kwang-Soo
authors: KS
authors: No
authors: Kijun
authors: K
authors: Lee
authors: Lee-Mi
authors: LM
authors: Do