title: Nanoscale two-bit/cell NAND silicon-oxide-nitride-oxide-silicon devices with a separated double-gate saddle-type structure.
abstract: Nanoscale two-bit/cell NAND silicon-oxide-nitride-oxide-silicon flash memory devices based on a separated double-gate (SDG) saddle structure with a recess channel region had two different doping regions in silicon-fin channel to operate two-bit per cell. A simulation results showed that the short channel effect, the cross-talk problem between cells, and the increase in threshold voltage distribution were minimized, resulting in the enhancement of the scaling-down characteristics and the program/erase speed.
authors: Department of Electronics and Computer Engineering, Hanyang University, Seoul 133-791, Korea.
authors: Sang Su
authors: SS
authors: Park
authors: Joo Hyung
authors: JH
authors: You
authors: Kae Dal
authors: KD
authors: Kwack
authors: Tae Whan
authors: TW
authors: Kim