title: Fabrication, characterization and simulation of high performance Si nanowire-based non-volatile memory cells.
abstract: We report the fabrication, characterization and simulation of Si nanowire SONOS-like non-volatile memory with HfO(2) charge trapping layers of varying thicknesses. The memory cells, which are fabricated by self-aligning in situ grown Si nanowires, exhibit high performance, i.e. fast program/erase operations, long retention time and good endurance. The effect of the trapping layer thickness of the nanowire memory cells has been experimentally measured and studied by simulation. As the thickness of HfO(2) increases from 5 to 30 nm, the charge trap density increases as expected, while the program/erase speed and retention remain the same. These data indicate that the electric field across the tunneling oxide is not affected by HfO(2) thickness, which is in good agreement with simulation results. Our work also shows that the Omega gate structure improves the program speed and retention time for memory applications.
authors.affiliation: Department of Electrical and Computer Engineering, George Mason University, Fairfax, VA 22030, USA.
authors.forename: Xiaoxiao
authors.initials: X
authors.lastname: Zhu
authors.forename: Qiliang
authors.initials: Q
authors.lastname: Li
authors.forename: Dimitris E
authors.initials: DE
authors.lastname: Ioannou
authors.forename: Diefeng
authors.initials: D
authors.lastname: Gu
authors.forename: John E
authors.initials: JE
authors.lastname: Bonevich
authors.forename: Helmut
authors.initials: H
authors.lastname: Baumgart
authors.forename: John S
authors.initials: JS
authors.lastname: Suehle
authors.forename: Curt A
authors.initials: CA
authors.lastname: Richter