title: Physical fault tolerance of nanoelectronics.
abstract: The error rate in complementary transistor circuits is suppressed exponentially in electron number, arising from an intrinsic physical implementation of fault-tolerant error correction. Contrariwise, explicit assembly of gates into the most efficient known fault-tolerant architecture is characterized by a subexponential suppression of error rate with electron number, and incurs significant overhead in wiring and complexity. We conclude that it is more efficient to prevent logical errors with physical fault tolerance than to correct logical errors with fault-tolerant architecture.
authors.affiliation: Department of Electrical and Computer Engineering, McGill University, Montréal, Québec H3A 2A7, Canada.
authors.forename: Thomas
authors.initials: T
authors.lastname: Szkopek
authors.forename: Vwani P
authors.initials: VP
authors.lastname: Roychowdhury
authors.forename: Dimitri A
authors.initials: DA
authors.lastname: Antoniadis
authors.forename: John N
authors.initials: JN
authors.lastname: Damoulakis