title: A multi-level capacitor-less memory cell fabricated on a nano-scale strained silicon-on-insulator.
abstract: A multi-level capacitor-less memory cell was fabricated with a fully depleted n-metal-oxide-semiconductor field-effect transistor on a nano-scale strained silicon channel on insulator (FD sSOI n-MOSFET). The 0.73% biaxial tensile strain in the silicon channel of the FD sSOI n-MOSFET enhanced the effective electron mobility to ∼ 1.7 times that with an unstrained silicon channel. This thereby enables both front- and back-gate cell operations, demonstrating eight-level volatile memory-cell operation with a 1 ms retention time and 12 µA memory margin. This is a step toward achieving a terabit volatile memory cell.
authors: National Program Center for Tera-bit-level Nonvolatile Memory Development, Department of Electronic Engineering, Hanyang University, Seoul, Republic of Korea. parkjgL@hanyang.ac.kr
authors: Jea-Gun
authors: JG
authors: Park
authors: Seong-Je
authors: SJ
authors: Kim
authors: Mi-Hee
authors: MH
authors: Shin
authors: Seung-Hyun
authors: SH
authors: Song
authors: Sung-Woong
authors: SW
authors: Chung
authors: Hirofumi
authors: H
authors: Enomoto
authors: Tae-Hun
authors: TH
authors: Shim