title: Bias stress effects on different dielectric surfaces of pentacene thin-film transistors.
abstract: In this paper, it was demonstrated that pentacene thin-film transistors (TFTs) were fabricated with an organic adhesion layer between an organic semiconductor and a gate insulator. In order to form polymeric film as an adhesion layer, a vapor deposition polymerization (VDP) process was introduced to substitute for the usual spin-coating process. Field effect mobility, threshold voltage, and on/off current ratio in pentacene TFTs with a 15 nm thick organic adhesion layer were about 0.4 cm2/Vs, -1 V, and 10(6), respectively. We also demonstrated that threshold voltage strongly depends on the stress time when a gate voltage has been applied for bias stress test. We suggest that a polyimide adhesion layer fabricated by the VDP method can be applied to realize organic TFTs with long-term stability because of lower threshold voltage shifts due to reduced charge trapping at the interface between the pentacene semiconductor and the polyimide layer.
authors.affiliation: Department of Materials Science and Engineering, Hongik University, Seoul, Korea.
authors.forename: Gun Woo
authors.initials: GW
authors.lastname: Hyung
authors.forename: Ja-Ryong
authors.initials: JR
authors.lastname: Koo
authors.forename: Ji Hoon
authors.initials: JH
authors.lastname: Seo
authors.forename: Jin Woo
authors.initials: JW
authors.lastname: Yang
authors.forename: Ho Won
authors.initials: HW
authors.lastname: Lee
authors.forename: Sang Woo
authors.initials: SW
authors.lastname: Pyo
authors.forename: Young Kwan
authors.initials: YK
authors.lastname: Kim