title: A simple device unit consisting of all NiO storage and switch elements for multilevel terabit nonvolatile random access memory.
abstract: Present charge-based silicon memories are unlikely to reach terabit densities because of scaling limits. As the feature size of memory shrinks to just tens of nanometers, there is insufficient volume available to store charge. Also, process temperatures higher than 800 °C make silicon incompatible with three-dimensional (3D) stacking structures. Here we present a device unit consisting of all NiO storage and switch elements for multilevel terabit nonvolatile random access memory using resistance switching. It is demonstrated that NiO films are scalable to around 30 nm and compatible with multilevel cell technology. The device unit can be a building block for 3D stacking structure because of its simple structure and constituent, high performance, and process temperature lower than 300 °C. Memory resistance switching of NiO storage element is accompanied by an increase in density of grain boundary while threshold resistance switching of NiO switch element is controlled by current flowing through NiO film.
authors: Semiconductor Device Laboratory, Samsung Advanced Institute of Technology, Gyeonggi 440-600, Korea. myoungjae.lee@samsung.com
authors: Myoung-Jae
authors: MJ
authors: Lee
authors: Seung-Eon
authors: SE
authors: Ahn
authors: Chang Bum
authors: CB
authors: Lee
authors: Chang-Jung
authors: CJ
authors: Kim
authors: Sanghun
authors: S
authors: Jeon
authors: U-In
authors: UI
authors: Chung
authors: In-Kyeong
authors: IK
authors: Yoo
authors: Gyeong-Su
authors: GS
authors: Park
authors: Seungwu
authors: S
authors: Han
authors: In Rok
authors: IR
authors: Hwang
authors: Bae-Ho
authors: BH
authors: Park