title: Parallel programmable asynchronous neighborhood mechanism for Kohonen SOM implemented in CMOS technology.
abstract: We present a new programmable neighborhood mechanism for hardware implemented Kohonen self-organizing maps (SOMs) with three different map topologies realized on a single chip. The proposed circuit comes as a fully parallel and asynchronous architecture. The mechanism is very fast. In a medium sized map with several hundreds neurons implemented in the complementary metal-oxide semiconductor 0.18   μm technology, all neurons start adapting the weights after no more than 11 ns. The adaptation is then carried out in parallel. This is an evident advantage in comparison with the commonly used software-realized SOMs. The circuit is robust against the process, supply voltage and environment temperature variations. Due to a simple structure, it features low energy consumption of a few pJ per neuron per a single learning pattern. In this paper, we discuss different aspects of hardware realization, such as a suitable selection of the map topology and the initial neighborhood range, as the optimization of these parameters is essential when looking from the circuit complexity point of view. For the optimal values of these parameters, the chip area and the power dissipation can be reduced even by 60% and 80%, respectively, without affecting the quality of learning.
authors: Faculty of Telecommunication and Electrical Engineering, University of Technology and Life Sciences, Bydgoszcz 85-796, Poland. rafal.dlugosz@gmail.com
authors: Rafał
authors: R
authors: Długosz
authors: Marta
authors: M
authors: Kolasa
authors: Witold
authors: W
authors: Pedrycz
authors: Michał
authors: M
authors: Szulc
mesh_terms: D003205:Computing Methodologies; D004867:Equipment Design; D019544:Equipment Failure Analysis; D016571:Neural Networks, Computer; D012815:Signal Processing, Computer-Assisted / Q000295:instrumentation*; D014173:Transistors, Electronic