title: High-side nLDMOS design for ensuring breakdown voltages over 100 V.
abstract: We propose a novel n-channel LDMOSFET (Lateral Double-diffused Metal Oxide Semiconductor Field Effect Transistor) structure with a breakdown voltage over 100 V under the thermal budget for the conventional 0.35 microm BCD process. We varied the gap between the DEEP N-WELL and the center of the source for optimization and optimized the doping concentration under the surface by the N(ADJUST)-layer in an effort to obtain high breakdown voltage and simultaneously the low specific on-resistance. The fabricated samples of the proposed High-Side n-channel LDMOS structure exhibit BVdss of 120 V and the specific on-resistance of 2.40 m ohms cm2. We also observed the shift of maximum impact ionization rate from the gate region to the drain side which is considered to strengthen the breakdown characteristics. The numerical simulation revealed that the maximum impact ionization rate of the proposed structure can be reduced down to 18.61 cm(-3) s(-1), while that of the conventional structure being as high as 25.44 cm(-3) s(-1).
authors: Department of Electrical Engineering, School of Engineering, Inha University, Incheon, 402-751, Korea.
authors: Kunsik
authors: K
authors: Sung
authors: Taeyoung
authors: T
authors: Won