title: Split-gate-structure 1T DRAM for retention characteristic improvement.
abstract: As the feature size of the conventional 1T-1C DRAM scales down, difficulties of the fabrication process are increasing and it is becoming harder to keep a constant capacitance value for data storage. Capacitor-less 1T DRAM is a promising candidate for the substitution of the conventional 1T-1C DRAM, but its poor retention time is one of the critical issues in its commercialization. In the selection of a bias condition for 1T DRAM, however, it is impossible to choose a gate bias condition that is suitable for both the "1" and "0" hold state data. In this paper, a split gate structure and hold bias scheme are proposed for the simultaneous improvement of the "1" and "0" data retention characteristics. It was confirmed through numerical simulation that this structure has a more than 3 sec retention time. A vertical gate-all-around split-gate structure and its fabrication method are also suggested to achieve high density, low cost, a higher sensing margin, and a longer retention time.
authors: Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering, Seoul National University, San 56-1, Shinlim-Dong, Kwanak-Gu, Seoul 151-742, Republic of Korea.
authors: Garam
authors: G
authors: Kim
authors: Sang Wan
authors: SW
authors: Kim
authors: Kyung-Chang
authors: KC
authors: Ryoo
authors: Jeong-Hoon
authors: JH
authors: Oh
authors: Min-Chul
authors: MC
authors: Sun
authors: Hyun Woo
authors: HW
authors: Kim
authors: Dae Woong
authors: DW
authors: Kwon
authors: Ji Soo
authors: JS
authors: Jang
authors: Sunghun
authors: S
authors: Jung
authors: Jang Hyun
authors: JH
authors: Kim
authors: Byung-Gook
authors: BG
authors: Park