title: An improved equivalent simulation model for CMOS integrated Hall plates.
abstract: An improved equivalent simulation model for a CMOS-integrated Hall plate is described in this paper. Compared with existing models, this model covers voltage dependent non-linear effects, geometrical effects, temperature effects and packaging stress influences, and only includes a small number of physical and technological parameters. In addition, the structure of this model is relatively simple, consisting of a passive network with eight non-linear resistances, four current-controlled voltage sources and four parasitic capacitances. The model has been written in Verilog-A hardware description language and it performed successfully in a Cadence Spectre simulator. The model's simulation results are in good agreement with the classic experimental results reported in the literature.
authors.affiliation: School of Electronic Science & Engineering, Nanjing University, Nanjing, China. yuex@njupt.edu.cn
authors.forename: Yue
authors.initials: Y
authors.lastname: Xu
authors.forename: Hong-Bin
authors.initials: HB
authors.lastname: Pan