title: Strained MOSFETs on ordered SiGe dots.
abstract: The potential of strained DOTFET technology is demonstrated. This technology uses a SiGe island as a stressor for a Si capping layer, into which the transistor channel is integrated. The structure information of fabricated samples is extracted from atomic force microscopy (AFM) measurements. Strain on the upper surface of a 30 nm thick Si layer is in the range of 0.7%, as supported by finite element calculations. The Ge content in the SiGe island is 30% on average, showing an increase towards the top of the island. Based on the extracted structure information, three-dimensional strain profiles are calculated and device simulations are performed. Up to 15% enhancement of the NMOS saturation current is predicted.
authors.affiliation: Institute for Microelectronics, Technische Universität Wien, Gusshausstraße 27-29, 1040 Wien, Austria.
authors.forename: Johann
authors.initials: J
authors.lastname: Cervenka
authors.forename: Hans
authors.initials: H
authors.lastname: Kosina
authors.forename: Siegfried
authors.initials: S
authors.lastname: Selberherr
authors.forename: Jianjun
authors.initials: J
authors.lastname: Zhang
authors.forename: Nina
authors.initials: N
authors.lastname: Hrauda
authors.forename: Julian
authors.initials: J
authors.lastname: Stangl
authors.forename: Guenther
authors.initials: G
authors.lastname: Bauer
authors.forename: Guglielmo
authors.initials: G
authors.lastname: Vastola
authors.forename: Anna
authors.initials: A
authors.lastname: Marzegalli
authors.forename: Francesco
authors.initials: F
authors.lastname: Montalenti
authors.forename: Leo
authors.initials: L
authors.lastname: Miglio