title: A 64-channel neuron recording system.
abstract: This paper presents a fully integrated low-power neuron recording front-end system in TSMC 65 nm 1p6m CMOS technology. The proposed system is comprised of two recording modules, each containing 32 recording channels with tunable bandwidth and gain, a 32-to-1 multiplexer, one differential successive approximation register (SAR) analog-to-digital converter (ADC) with programmable sampling rate on each channel, and a digital control module to govern the signal digitization as well as to encode and serialize the digitized neuron signal from two ADCs. The recording amplifier presents a low power and low noise merits of 6 μW and input-referred noise of 3.8 μV(rms). The ADC digitizes the neural signal at a sampling rate of 40 kS/s with 9-bit resolution. The overall power consumption of the entire system is 2.56 mW and occupies an area of 3 × 4mm(2).
authors.affiliation: Electrical Engineering Department, University of California, Santa Cruz, CA 95064, USA. yikai@soe.ucsc.edu
authors.forename: Yi-Kai
authors.initials: YK
authors.lastname: Lo
authors.forename: Wentai
authors.initials: W
authors.lastname: Liu
authors.forename: Kuanfu
authors.initials: K
authors.lastname: Chen
authors.forename: Ming-Hsien
authors.initials: MH
authors.lastname: Tsai
authors.forename: Fu-Lung
authors.initials: FL
authors.lastname: Hsueh
mesh_terms: D004867:Equipment Design; D009474:Neurons / Q000502:physiology*