title: Modular particle filtering FPGA hardware architecture for brain machine interfaces.
abstract: As the computational complexities of neural decoding algorithms for brain machine interfaces (BMI) increase, their implementation through sequential processors becomes prohibitive for real-time applications. This work presents the field programmable gate array (FPGA) as an alternative to sequential processors for BMIs. The reprogrammable hardware architecture of the FPGA provides a near optimal platform for performing parallel computations in real-time. The scalability and reconfigurability of the FPGA accommodates diverse sets of neural ensembles and a variety of decoding algorithms. Throughput is significantly increased by decomposing computations into independent parallel hardware modules on the FPGA. This increase in throughput is demonstrated through a parallel hardware implementation of the auxiliary particle filtering signal processing algorithm.
authors.affiliation: Electrical & Computer Engineering, Temple University, Philadelphia, PA, USA.
authors.forename: John
authors.initials: J
authors.lastname: Mountney
authors.forename: Iyad
authors.initials: I
authors.lastname: Obeid
authors.forename: Dennis
authors.initials: D
authors.lastname: Silage
mesh_terms: D001921:Brain / Q000502:physiology*; D003201:Computers; D006801:Humans; D008328:Man-Machine Systems