title: 100-Gbps CMOS transceiver for multilane optical backplane system with a 1.3 cm2 footprint.
abstract: A compact 4 × 25 Gbps optical transceiver has been fabricated for an optical backplane system, which consists of a 4 × 25 Gbps DFB-LD array, a 4 × 25 Gbps PIN-PD array, and a CMOS transceiver chip. These are directly mounted on 9 × 14 mm(2) multi-layer ceramic package with an electromagnetic shield structure to suppress inner-channel crosstalk effectively. The transceiver includes an analog front-end as well as an electrical interface function to interface with the switch LSI or CPU. Power consumption was as low as 20 mW/Gbps, and a transmission experiment was successfully conducted at 25 Gbps.
authors.affiliation: Central Research Laboratory, Hitachi, Ltd., 1-280, Higachi-koigakubo, Kokubunji-shi, Tokyo 185-8601, Japan. takashi.takemoto.tj@hitachi.com
authors.forename: Takashi
authors.initials: T
authors.lastname: Takemoto
authors.forename: Fumio
authors.initials: F
authors.lastname: Yuki
authors.forename: Hiroki
authors.initials: H
authors.lastname: Yamashita
authors.forename: Shinji
authors.initials: S
authors.lastname: Tsuji
authors.forename: Yong
authors.initials: Y
authors.lastname: Lee
authors.forename: Koichiro
authors.initials: K
authors.lastname: Adachi
authors.forename: Kazunori
authors.initials: K
authors.lastname: Shinoda
authors.forename: Yasunobu
authors.initials: Y
authors.lastname: Matsuoka
authors.forename: Kenji
authors.initials: K
authors.lastname: Kogo
authors.forename: Shinji
authors.initials: S
authors.lastname: Nishimura
authors.forename: Masaaki
authors.initials: M
authors.lastname: Nido
authors.forename: Masahiko
authors.initials: M
authors.lastname: Namiwaka
authors.forename: Taro
authors.initials: T
authors.lastname: Kaneko
authors.forename: Takara
authors.initials: T
authors.lastname: Sugimoto
authors.forename: Kazuhiko
authors.initials: K
authors.lastname: Kurata