title: Reduced distribution of threshold voltage shift in double layer NiSi2 nanocrystals for nano-floating gate memory applications.
abstract: We report on the fabrication and capacitance-voltage characteristics of double layer nickel-silicide nanocrystals with Si3N4 interlayer tunnel barrier for nano-floating gate memory applications. Compared with devices using SiO2 interlayer, the use of Si3N4 interlayer separation reduced the average size (4 nm) and distribution (+/- 2.5 nm) of NiSi2 nanocrystal (NC) charge traps by more than 50% and giving a two fold increase in NC density to 2.3 x 10(12) cm(-2). The increased density and reduced NC size distribution resulted in a significantly decrease in the distribution of the device C-V characteristics. For each program voltage, the distribution of the shift in the threshold voltage was reduced by more than 50% on average to less than 0.7 V demonstrating possible multi-level-cell operation.
authors.affiliation: Department of Nanoscale Semiconductor Engineering, Hanyang University, 17 Haengdangdong, Seongdonggu, Seoul 133-791, Korea.
authors.forename: Sungjin
authors.initials: S
authors.lastname: Choi
authors.forename: Junhyuk
authors.initials: J
authors.lastname: Lee
authors.forename: Donghyoun
authors.initials: D
authors.lastname: Kim
authors.forename: Seulki
authors.initials: S
authors.lastname: Oh
authors.forename: Wangyu
authors.initials: W
authors.lastname: Song
authors.forename: Seonjun
authors.initials: S
authors.lastname: Choi
authors.forename: Eunsuk
authors.initials: E
authors.lastname: Choi
authors.forename: Seung-Beck
authors.initials: SB
authors.lastname: Lee