A neuro-inspired spike-based PID motor controller for multi-motor robots with low cost FPGAs.
In this paper we present a neuro-inspired spike-based close-loop controller written in VHDL and implemented for FPGAs. This controller has been focused on controlling a DC motor speed, but only using spikes for information representation, processing and DC motor driving. It could be applied to other motors with proper driver adaptation. This controller architecture represents one of the latest layers in a Spiking Neural Network (SNN), which implements a bridge between robotics actuators and spike-based processing layers and sensors. The presented control system fuses actuation and sensors information as spikes streams, processing these spikes in hard real-time, implementing a massively parallel information processing system, through specialized spike-based circuits. This spike-based close-loop controller has been implemented into an AER platform, designed in our labs, that allows direct control of DC motors: the AER-Robot. Experimental results evidence the viability of the implementation of spike-based controllers, and hardware synthesis denotes low hardware requirements that allow replicating this controller in a high number of parallel controllers working together to allow a real-time robot control.
Deparment of Computer Architecture and Technology, Universidad de Sevilla, ETSI Informátca, Avd. Reina Mercedes s/n, 41012 Sevilla, Spain.
Angel
A
Jimenez-Fernandez
Deparment of Computer Architecture and Technology, Universidad de Sevilla, ETSI Informátca, Avd. Reina Mercedes s/n, 41012 Sevilla, Spain.
Gabriel
G
Jimenez-Moreno
Deparment of Computer Architecture and Technology, Universidad de Sevilla, ETSI Informátca, Avd. Reina Mercedes s/n, 41012 Sevilla, Spain.
Alejandro
A
Linares-Barranco
Deparment of Computer Architecture and Technology, Universidad de Sevilla, ETSI Informátca, Avd. Reina Mercedes s/n, 41012 Sevilla, Spain.
Manuel J
0000-0001-5669-9111
MJ
Dominguez-Morales
Deparment of Computer Architecture and Technology, Universidad de Sevilla, ETSI Informátca, Avd. Reina Mercedes s/n, 41012 Sevilla, Spain.
Rafael
R
Paz-Vicente
Deparment of Computer Architecture and Technology, Universidad de Sevilla, ETSI Informátca, Avd. Reina Mercedes s/n, 41012 Sevilla, Spain.
Anton
0000-0001-8733-1811
A
Civit-Balcells