III-V complementary metal-oxide-semiconductor electronics on silicon substrates.
One of the major challenges in further advancement of III-V electronics is to integrate high mobility complementary transistors on the same substrate. The difficulty is due to the large lattice mismatch of the optimal p- and n-type III-V semiconductors. In this work, we employ a two-step epitaxial layer transfer process for the heterogeneous assembly of ultrathin membranes of III-V compound semiconductors on Si/SiO(2) substrates. In this III-V-on-insulator (XOI) concept, ultrathin-body InAs (thickness, 13 nm) and InGaSb (thickness, 7 nm) layers are used for enhancement-mode n- and p- MOSFETs, respectively. The peak effective mobilities of the complementary devices are ∼1190 and ∼370 cm(2)/(V s) for electrons and holes, respectively, both of which are higher than the state-of-the-art Si MOSFETs. We demonstrate the first proof-of-concept III-V CMOS logic operation by fabricating NOT and NAND gates, highlighting the utility of the XOI platform.
Electrical Engineering and Computer Sciences, University of California, Berkeley, California 94720, United States.
Junghyo
J
Nah
Hui
H
Fang
Chuan
C
Wang
Kuniharu
K
Takei
Min Hyung
MH
Lee
E
E
Plis
Sanjay
S
Krishna
Ali
A
Javey